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low distortion, docsis 3.0, upstream catv line driver ADA4320-1 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2010 analog devices, inc. all rights reserved. features supports cablelabs? docsis 3.0/2.0 and eurodocsis 3.0/2.0 specifications for customer premises equipment (cpe) upstream transmission 5 v single-supply operation excellent adjacent channel rejection performance ?66 dbc acpr for a single qpsk channel ?63 dbc acpr for 4 qam64 channels gain programmable in 1 db steps over a 59 db range gain range: ?27 db to +32 db current-scaled output stage low between-burst output noise level ?70 db mv in 160 khz bandwidth maintains constant output impedance in enable, disable, and sleep conditions selectable low power modes 12 ma in tx disable 12 a in sleep mode (full power-down) 3-wire, spi-compatible interface 4 mm 5 mm 24-lead lfcsp, rohs compliant applications docsis 3.0 and eurodocsis cable modems/e-mtas docsis 3.0 set-top boxes catv telephony modems coaxial or twisted pair line drivers functional block diagram power amp diff or single input amp vernier vin? clk sdata gnd vin+ vout+ vout? ramp attenuation core decode data latch shift register 8 8 8 ADA4320-1 z out diff = 300 ? z in (single) = 320 ? z in (diff) = 640 ? power-down logic daten txen sleep 08707-001 figure 1. general description the ADA4320-1 is a high power, ultralow distortion amplifier designed for catv reverse channel line driving. its features and specifications make the ADA4320-1 ideally suited for docsis 3.0- and eurodocsis 3.0-based applications. both gain and output stage current are controlled via a 3-wire (spi-compatible) interface. a single 8-bit serial word selects one of four available supply current presets and one of sixty gain codes. the ADA4320-1 has been tailored to address both the high output drive and stringent fidelity requirements of docsis 3.0. the part is able to maintain excellent adjacent channel rejection performance over the full 5 mhz to 85 mhz range, even with multiple bonded channels at maximum specified output levels. the ADA4320-1 accepts a differential or single-ended input signal. the output is specified for driving a single-ended 75 load through a 4:1 impedance transformer. the ADA4320-1 features an output driver stage that scales quiescent current consumption according to gain setting. in multichannel mode at maximum gain (32 db), the device draws 260 ma from a single 5 v supply, enabling the high power, ultralow distortion performance required by multiple docsis 3.0 upstream channels. for lifeline e-mta applications, the ADA4320-1 output stage current can be throttled via spi commands, reducing the power requirement for single-channel transmission by up to 30%. in transmit-disable mode, the ADA4320-1 draws only 12 ma. the device also features a full power-down sleep mode that further reduces current draw to12 a typical. the ADA4320-1 is packaged in a rohs-compliant, 24-lead exposed pad lfcsp and is rated for operation over the ?40c to +85c temperature range.
ADA4320-1 rev. a | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 logic inputs (ttl-/cmos-compatible logic) ....................... 4 timing requirements .................................................................. 5 absolute maximum ratings ............................................................ 6 thermal resistance ...................................................................... 6 maximum power dissipation ..................................................... 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 applications information .............................................................. 11 general applications ................................................................. 11 circuit description .................................................................... 11 programming .............................................................................. 11 current level and gain adjustment ....................................... 11 power saving features ............................................................... 12 input bias, impedance, and termination ................................ 12 output bias, impedance, and termination ............................ 12 power supply ............................................................................... 12 signal integrity layout considerations ................................... 12 initial power-up ......................................................................... 12 ramp pin feature ..................................................................... 13 output transformer ................................................................... 13 outline dimensions ....................................................................... 14 ordering guide .......................................................................... 14 revision history 10/10rev. 0 to rev. a changes to product title ................................................................. 1 changes to pin 14, description, table 6 ........................................ 7 changes to current level and gain adjustment section ......... 11 changes to output bias, impedance, and termination section ....................................................................... 12 changes to figure 24 ...................................................................... 13 changes to ordering guide .......................................................... 14 4/10revision 0: initial version
ADA4320-1 rev. a | page 3 of 16 specifications t a = 25c, v s = 5 v, r l = 75 , v in (differential) = 29 db mv sinusoidal, f = 5 mhz to 85 mhz, gain, v out (single-ended) measured at output of coilcraft pwb-4-bl transformer, unless otherwise noted. table 1. parameter conditions min typ max unit input characteristics input resistance balanced (differential) input 640 unbalanced (single- ended) input 320 input capacitance 2.0 pf gain control current level 3 gain range 57.5 59 60 db maximum gain gain code 60 30.5 32 db minimum gain gain code 01 ?27 ?25.5 db output step size 0.6 1.0 1.4 db/lsb output characteristics gain flatness referenced to 10 mhz at maximum gain f = 42 mhz, gain code 60, current level 3 ?0.3 db f = 65 mhz, gain code 60, current level 3 ?0.7 db f = 85 mhz, gain code 60, current level 3 ?1.1 db at minimum gain f = 42 mhz, gain code 01, current level 0 ?0.4 db f = 65 mhz, gain code 01, current level 0 ?0.8 db f = 85 mhz, gain code 01, current level 0 ?1.8 db 1 db compression point (p 1db ) f = 10 mhz, gain code 60, current level 3, output referred 70 db mv output noise in 160 khz bandwidth f = 10 mhz, 294 resistor across vin+ and vin? pins at maximum gain gain code 60, current level 3, txen = high (1) ?19 ?20 db mv gain code 60, current level 0, txen = high (1) ?20 ?21 db mv at minimum gain gain code 01, current level 3, txen = high (1) ?59 ?60 db mv gain code 01, current level 0, txen = high (1) ?60 ?61 db mv transmit disabled txen = low (0) ?68 ?70 db mv output impedance (measured at transformer output) txen = high (1) or txen = low (0) or sleep = low (0) 75 output return loss (measured at transformer output) f = 85 mhz sleep = high (1), txen = high (1) 12 db sleep = high (1), txen = low (0) 11 db sleep = low (0) 10 db overall performance adjacent channel power ratio (acpr) single qpsk channel f = 5 mhz to 85 mhz, output level = 61 db mv, gain code 60, current level 3, channel width = 6.4 mhz, adjacent channel width = 6.4 mhz ?66 dbc 4x qam64 channels f = 5 mhz to 85 mhz, output level = 53 db mv/channel, gain code 60, current level 3, channel width = 1.6 mhz, adjacent channel width = 1.6 mhz ?63 dbc output third-order intercept point (oip3) f 1 = 84 mhz, f 2 = 85 mhz, gain code 60, current level 3 93 db mv f 1 = 84 mhz, f 2 = 85 mhz, gain code 60, current level 0 87 db mv input-to-output isolation f = 85 mhz, gain code 60, txen = low (0) 107 db
ADA4320-1 rev. a | page 4 of 16 parameter conditions min typ max unit power control transmit enable settling time txen = 0 to 1, gain code 60, no input signal 5.5 s transmit disable settling time txen = 1 to 0, gain code 60, no input signal 7 s output switching transients gain code 60 20 mv p-p gain code 01 2 mv p-p power supply operating range 4.75 5.00 5.25 v quiescent current at maximum gain gain code 60, current level 3 260 300 ma gain code 60, current level 2 235 270 ma gain code 60, current level 1 210 250 ma gain code 60, current level 0 180 210 ma at minimum gain gain code 01, current level 3 77 100 ma gain code 01, current level 2 73 95 ma gain code 01, current level 1 70 90 ma gain code 01, current level 0 65 80 ma txen = 0, all gain codes, all current levels 12 15 ma sleep = 0 (power-down) 12 80 a operating temperature range ?40 +85 c logic inputs (ttl-/cmos-compatible logic) daten , clk, sdata, txen, sleep , v s = 5 v; full temperature range. table 2. parameter min typ max unit logic 1 voltage 2.0 v s v logic 0 voltage 0 0.8 v digital input leakage current (both logic levels, all digital pins) ?5 +5 a
ADA4320-1 rev. a | page 5 of 16 timing requirements full temperature range, v cc = 5 v, t r = t f = 4 ns, f clk = 8 mhz, unless otherwise noted. table 3. parameter min typ max unit clock pulse width (t wh ) 16 ns clock period (t c ) 32 ns setup time sdata vs. clock (t ds ) 5 ns setup time daten vs. clock (t es ) 16 ns hold time sdata vs. clock (t dh ) 5 ns hold time daten vs. clock (t eh ) 3 ns input 10% to 90% rise and fall times, sdata, daten , clock 10 ns valid data-word g1 msb...lsb valid data-word g2 sdata clk txen a nalog output daten t ds t es t eh 8 clock cycles gain transfer (g1) gain transfer (g2) t wh t c signal amplitude (p-p) 08707-002 figure 2. serial interface timing sdata msb msb ? 1 msb ? 2 clk valid data bit t ds t dh 08707-003 figure 3. sdata timing
ADA4320-1 rev. a | page 6 of 16 absolute maximum ratings maximum power dissipation table 4. parameter rating supply voltage 5.5 v maximum power dissipation 1.65 w storage temperature range ?65c to +125c operating temperature range ?40c to +85c lead temperature (soldering, 10 sec) 300c junction temperature 150c the maximum safe power dissipation in the ADA4320-1 package is limited by the associated rise in junction temperature (t j ) on the die. at approximately 150c, which is the glass transition temperature, the plastic changes its properties. even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ADA4320-1. exceeding a junction temperature of 150c for an extended time can result in changes in the silicon devices, potentially causing failure. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. airflow increases heat dissipation, effectively reducing ja . in addition, more metal directly in contact with the package leads from metal traces, through-holes, ground, and power planes, reduces the ja . the exposed paddle on the underside of the package must be soldered to a pad on the pcb surface that is thermally connected to a copper plane to achieve the specified ja . thermal resistance ja is specified for the device soldered to a high thermal conductivity 4-layer (2s2p) circuit board, as described in eia/jesd 51-7. esd caution table 5. thermal resistance package type ja jc unit 24-lead lfcsp 31.2 5.7 c/w
ADA4320-1 rev. a | page 7 of 16 pin configuration and fu nction descriptions 82 92 10 22 11 21 12 gnd gnd vin? vin+ gnd 20 comp vout 4 3 + vout ? vout + vout ? 19 18 17 16 15 14 1 2 3 4 5 6 7 gnd gnd vcc vcc vcc ramp txen 13 gnd gnd gnd sleep clk sdata daten ADA4320-1 top view (not to scale notes 1. exposed thermal pad must be electrically and thermally connected to pcb ground (gnd) plane. 08707-005 figure 4. pin configuration, top view table 6. pin function descriptions pin no. mnemonic description 1, 2, 8, 9, 12, 17, 18, 19, epad gnd common external ground reference. 3, 4, 5 vcc common positive external supply voltage. 6 ramp external ramp capacitor (optional). 7 txen transmit enable. logic 0 disables forward tran smission, and logic 1 enables forward transmission. 10 vin? inverting input. dc-biased to approximately v cc /2. this pin should be ac-coupled with a 0.1 f capacitor. 11 vin+ noninverting input. dc-biased to approximately v cc /2. this pin should be ac-coupled with a 0.1 f capacitor. 13 daten data enable low input. this port controls the 8-bit parallel data latch and shift register. a logic 0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and simultaneously inhibits serial data transfer into the register. a 1-to-0 transition inhibits the data latch (holds the previous, and simultaneously enables the register for serial data load). 14 sdata serial data input. this digital input allows an 8-bit serial co ntrol word to be loaded into the internal register with the most significant bit (msb) first to adjust both the gain and current levels. 15 clk clock input. the clock port controls the serial attenuator data transfer rate to the 8-bit master-slave shift register. a logic 0-to-1 transition latches the data bit, and a logic 1-to-0 transition transfers the data bit to the slave. this requires the input serial data-word to be va lid at or before this clock transition. 16 sleep low power sleep mode. in sleep mode, the supply current is reduced to 12 a typical. logic 0 powers down the device, and logic 1 powers up the device. 20, 22 vout? negative output signal. this pin must be biased to v cc . 21, 23 vout+ positive output signal. this pin must be biased to v cc . 24 comp internal compensation. this pin must be externally decoupled (0.1 f capacitor).
ADA4320-1 rev. a | page 8 of 16 typical performance characteristics t a = 25c, v s = 5 v, r l = 75 , v in (differential) = 29 dbmv sinusoidal, f = 5 mhz to 85 mhz, gain code 60 (maximum), current level 3 (maximum), v out (single-ended) measured at output of coilcraft pwb-4-bl transformer, unless otherwise noted. 300 50 100 150 200 250 0 6 12 18 24 30 36 42 48 54 60 supply current (ma) gain code current level 3 current level 2 current level 1 current level 0 v in = 29dbmv 08707-006 figure 5. supply current vs. gain code 275 270 265 260 255 250 245 240 235 ?60 ?40 ?20 0 20 40 60 80 100 supply current (ma) ambient temperature (c) gain code 60 current level 3 5.25v 5.00v 4.75v 08707-007 figure 6. supply current vs. ambient temperature at maximum gain 75 70 65 60 55 50 ?60 ?40 ?20 0 20 40 60 80 100 supply current (ma) ambient temperature (c) gain code 01 current level 0 5.25v 5.00v 4.75v 08707-008 figure 7. supply current vs. ambient temperature at minimum gain 60 ?60 ?45 ?30 ?15 0 15 30 45 1m 1g 100m 10m gain (db) frequency (hz) current level 3 v in = 29dbmv gain code 60 gain code 40 gain code 20 gain code 01 08707-009 figure 8. gain vs. frequency 1.0 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 58 807570656055 50 45403530 25 201510 normalized gain (db) frequency (mhz) 5 current level 3 current level 2 current level 1 current level 0 gain code 60 (maximum) v in = 29dbmv 08707-010 figure 9. normalized frequenc y response at maximum gain 1.0 ?3.0 ?2.0 ?2.5 ?1.5 ?1.0 ?0.5 0 0.5 58 807570656055 50 45403530 25 201510 normalized gain (db) frequency (mhz) 5 +25c ?40c +85c gain code 60 (maximum) v in = 29dbmv 08707-011 figure 10. normalized frequency response over temperature
ADA4320-1 rev. a | page 9 of 16 ? 10 ?80 ?70 ?60 ?50 ?40 ?30 ?20 06 0 544842 36 3024 18 12 6 noise power in 160khz bandwidth (dbmv) gain code txen = 1, all current l evels txen = 0 08707-013 figure 11. noise power vs. gain code 0 ?30 ?25 ?20 ?15 ?10 ?5 58 5 807570656055 50 45403530 25 201510 output return loss (db) frequency (mhz) sleep tx disable tx enable 08707-012 figure 12. output return loss (s22) vs. frequency ? 61 ?62 ?63 ?64 ?65 ?66 ?67 ?68 58 5 7565554535 25 15 adjacent channel power ratio (dbc) frequency (mhz) current level 0 current level 1 current level 2 current level 3 single qpsk channel output level = 61dbmv gain code 60 (maximum) channel width = 6.4mhz adjacent channel width = 6.4mhz 08707-015 figure 13. acpr vs. frequenc y for single qpsk channel 80 20 30 40 50 60 70 06 544842 36 30241812 6 output 1db compression point (dbmv) gain code 0 current level 3 current level 0 08707-014 figure 14. output 1 db comp ression point vs. gain code ? 40 ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 80 0 10 20 30 40 50 60 70 adjacent channel power ratio (dbc) output level (dbmv) 06 54 48423630241812 6 gain code output level acpr 0 single qpsk channel input level = 29dbmv current level 3 channel width = 6.4mhz driven channel center = 42mhz adjacent channel width = 6.4mhz adjacent channel center = 48.4mhz 08707-017 figure 15. acpr and output level vs. gain code ? 52 ?54 ?56 ?58 ?60 ?62 ?64 ?66 58 7565554535 25 15 adjacent channel power ratio (dbc) frequency (mhz) 5 current level 0 current level 1 current level 2 current level 3 4 qam64 channels (uncorrelated) output level = 53dbmv/channel gain code 60 (maximum) channel width = 1.6mhz adjacent channel width = 1.6mhz 08707-016 figure 16. acpr vs. frequency for 4 qam64 channels
ADA4320-1 rev. a | page 10 of 16 ?24 ?28 ?32 ?36 ?40 ?44 ?48 ?52 ?56 ?60 ?64 ?68 ?72 adjacent channel power ratio (dbc) 25 42 41403938373635343332313029282726 input level (dbmv) current level 0 current level 1 current level 2 current level 3 single qpsk channel gain code 42 (14db) channel width = 6.4mhz driven channel center = 42 mhz adjacent channel width = 6.4 mhz adjacent channel center = 48.4 mhz 08707-018 figure 17. acpr vs. input level for a single qpsk channel ?10 ?80 ?70 ?60 ?50 ?40 ?30 ?20 adjacent channel power ratio (dbc) 59 71 70 69 686766656463626160 output level (dbmv) current level 0 current level 1 current level 2 current level 3 single qpsk channel gain code 60 (maximum) channel width = 6.4mhz driven channel center = 42mhz adjacent channel width = 6.4mhz adjacent channel center = 48.4mhz 08707-020 figure 18. acpr vs. output level for a single qpsk channel 8 6 ?8 ?6 ?4 ?2 0 2 4 output amplitude (v) ?2 18 14 16 12 10 86420 time (s) 4 qam64 channels (uncorrelated) output level = 53dbmv/channel channel width = 1.6mhz channel centers = 39.6mhz, 41.2mhz, 42.8mhz, 44.4mhz) txen peak output envelope 08707-022 figure 19. transmit enable/disable response ?22 ?70 ?64 ?58 ?52 ?46 ?40 ?34 ?28 adjacent channel power ratio (dbc) 12 31 29 302827262524 23 22 21 2019181716151413 input level (dbmv/channel) current level 0 current level 1 current level 2 current level 3 4 qam64 channels (uncorrelated) gain code 42 (14db) channel width = 1.6mhz driven channel center = 77.8mhz, 79.4mhz, 81.0mhz, 82.6mhz adjacent channel width = 1.6mhz adjacent channel center = 84.2mhz 08707-019 figure 20. acpr vs. input level for 4 qam64 channels ?10 ?80 ?70 ?60 ?50 ?40 ?30 ?20 adjacent channel power ratio (dbc) 44 62 605856 54 52504846 output level (dbmv/channel) current level 0 current level 1 current level 2 current level 3 4 qam64 channels (uncorrelated) gain code 60 (maximum) channel width = 1.6mhz driven channel center = 77.8mhz, 79.4mhz, 81.0mhz, 82.6mhz adjacent channel width = 1.6mhz adjacent channel center = 84.2mhz 08707-021 figure 21. acpr vs. output level for 4x qam64 channels 120 100 80 60 40 20 0 output glitch amplitude (mv p-p) 06 48 54 42 36 30241812 6 gain code 0 txen = 1 txen = 0 docsis 3.0 limit (for 29dbmv input) 08707-023 figure 22. output glitch amplitude vs. gain code
ADA4320-1 rev. a | page 11 of 16 applications information general applications the ADA4320-1 is primarily intended for use as the reverse channel power amplifier (pa) in docsis? 3.0 customer premises equipment (cpe), including cable modems, e-mtas, and docsis-enabled set-top boxes. the signals are typically qpsk or qam waveforms generated by the upstream modulator and dac. to sufficiently attenuate dac images, a low-pass reconstruction filter is recommended between the dac output and the ADA4320-1. a differential filter is preferred, and its output impedance should match the 640 input impedance of the ADA4320-1. varying distances between the cpe and the cable modem termination system (cmts), as well as diplexers and splitters that may exist in the signal path, require the amplifier to provide a wide range of output power. the combination of a high output level, excellent linearity, and 59 db gain range of the ADA4320-1 enables the cpe to overcome inline losses and ensures adequate signal strength at the upstream termination. circuit description in power-up mode, the ADA4320-1 comprises three analog functions. the input amplifier (preamp) can be used single-ended or balanced (differential). if the input is used in the balanced configuration, it is imperative that the input signals be 180 out of phase and of equal amplitude. a vernier adjustment amplifier controls the 1 db gain steps. the digital attenuator (da) stage provides coarse adjustment in 6 db steps. it also scales the current supplied to the output stage. both the preamp and da are differential (balanced) to improve power supply rejection and linearity. the differential current is output from the da to the output stage. the output stage, with its 300 balanced output impedance, maintains proper matching to a 75 load when used with a 2:1 (turns ratio) balun transformer. programming the ADA4320-1 is controlled via a unidirectional, 3-wire serial interface (spi-compatible) consisting of clk, daten , and sdata signals. an 8-bit data-word containing the output stage current level (bits[7:6]) and desired gain code (bits[5:0]) is clocked into the sdata port, msb first. the programmable current level (cl) range of the ADA4320-1 is cl3 (highest) to cl0 (lowest). the programmable gain range is +32 db (gain code 60) to ?27 db (gain code 01), in steps of 1 db per least significant bit (lsb), providing a total gain range of 59 db. table 7. data-word for setting current and gain levels cl typical current (ma) cl[7:6] (bin) gain[5:0] (hex) cain code (dec) typical gain (db) 3 260 to 77 11 3c to 01 60 to 01 +32 to ?27 2 235 to 73 10 3c to 01 60 to 01 +32 to ?27 1 210 to 70 01 3c to 01 60 to 01 +32 to ?27 0 180 to 65 00 3c to 01 60 to 01 +32 to ?27 the sequence of loading the sdata register starts on the falling edge of the daten pin, which activates the clk line. data on the sdata line is clocked into the serial shift register on the rising edge of clk, msb first. the data-word is latched into the attenuator core on the rising edge of daten . serial interface timing for the ADA4320-1 is shown in and . figure 2 figure 3 current level and gain adjustment gain adjustment and current scaling allow the pa to achieve the high output levels and linearity required for multiple-channel docsis 3.0 compliance, while offering significantly reduced power consumption in single-channel and lifeline battery-backup modes of operation. there are two methods used to adjust the supply current of the ADA4320-1. the four curves in figure 23 represent the supply current vs. gain code for the different current level (cl3 to cl0). the current levels are selectable using bit 6 and bit 7 of the 8-bit control word clocked into the serial data port. in addition to the selectable current levels, the supply current is automatically reduced for every 6 db reduction in gain. at higher gain settings, this is more pronounced. at maximum gain setting and maximum current level, a step down of 6 db reduces the supply current by 33%. 300 50 100 150 200 250 30 ?30 ?18 ?6 6 18 0 1224364860 supply current (ma) gain (db) gain code current level 3 current level 2 current level 1 current level 0 gain 08707-024 figure 23. gain and current scaling
ADA4320-1 rev. a | page 12 of 16 power saving features the ADA4320-1 incorporates three distinct methods for reducing power consumption that include the following: ? transmit disable for between-burst periods ? sleep (shutdown) mode ? output stage current scaling the asynchronous txen pin is used to place the ADA4320-1 into between-burst mode. in this reduced current state, the 300 differential output impedance is maintained. applying logic 0 to the txen pin deactivates the amplifier, providing up to 95% reduction in consumed power. for 5 v operation at maximum gain and current level, supply current is typically reduced from 260 ma to 12 ma. in this mode of operation, between-burst noise is minimized and over 100 db of input to output isolation is achieved. additionally, the ADA4320-1 incorporates an asynchronous sleep pin that can be used to further reduce supply current to approximately 12 a. applying logic 0 to the sleep pin places the amplifier into sleep mode. entering/exiting sleep mode can result in a transient voltage at the output of the amplifier. it is recommended to perform transitions on the sleep pin with txen held low. additional power savings are possible by optimizing the output stage current for different operating conditions. typically, at lower frequencies (5 mhz to 42 mhz), the full specified output can be maintained in cl0 (see figure 13 and figure 16 ). for lower input levels, the same is true, as shown in figure 17 and figure 20 . for per-channel output levels less than 65 dbmv (qpsk) and 50 dbmv (4 qam64), the ADA4320-1 can maintain an acpr of better than ?60 dbc (see figure 18 and figure 21 ) at current level 0 (cl0). at higher gain settings, operating in cl0 reduces current consumption by 30%, compared to operating in cl3. as an example, operating in cl0, the ADA4320-1 can drive a single qpsk channel at 61 dbmv, at maximum gain, maintaining a worst-case acpr of ?66 dbc. it does this while drawing only 180 ma from a 5 v supply. input bias, impedance, and termination the vin+ and vin? inputs have a dc bias level of v cc /2; therefore, the input signal should be ac-coupled as seen in the typical application circuit (see figure 24 ). the differential input impedance of the ADA4320-1 is approximately 640 , and the single-ended input is 320 . the ADA4320-1 exhibits optimum performance when driven with a balanced (differential) signal. output bias, impedance, and termination the output stage of the ADA4320-1 requires a bias of 5 v. the 5 v power supply should be applied to the center tap of the output transformer through a 100 nh series inductor as shown in figure 24 . the 100 nh inductor should be placed close to the transformer center tap to reduce parasitic capacitance on this node and to obtain best performance. the output impedance of the ADA4320-1 is 300 differential, regardless of whether the amplifier is in transmit enable, transmit disable, or sleep mode. this, when combined with a 4:1 impedance transformer, provides a 75 output match and eliminates the need for external back termination resistors. if the output signal is being evaluated using standard 50 test equipment, a minimum loss 75 to 50 pad should be used to provide the test circuit with the proper impedance match. power supply the 5 v supply should be delivered to each of the vcc pins via a low impedance power bus. the power bus should be decoupled with a 10 f tantalum capacitor located close to the ADA4320-1. additionally, the vcc pins require decoupling to ground with ceramic chip capacitors located close to the pins. pin 24 (comp), should also be decoupled. the ideal printed circuit board (pcb) has a low impedance ground plane covering all unused portions of the board, except in areas of the board where input and output traces are in close proximity to the ADA4320-1 and the output transformer. all device gnd pins, as well as the exposed pad, must contact the pcb ground plane to ensure proper grounding of all internal nodes. signal integrity layout considerations careful attention to pcb layout details can prevent problems due to board parasitics. proper rf design techniques are highly recommended. all balanced input/output traces should be kept as short as possible. this minimizes parasitic capacitance and inductance, which is most critical between the outputs of the ADA4320-1 and the 4:1 output transformer. it is also recommended that all balanced signal paths be symmetrical in length and width. additionally, input and output traces should be adequately spaced to minimize coupling (crosstalk) through the board. following these guidelines optimizes the overall performance of the ADA4320-1 in all applications. initial power-up when supply voltage is applied to the ADA4320-1, the gain of the amplifier is initially undetermined. during amplifier power- up, the txen pin should be held low (logic 0) to prevent forward signal transmission. gain must then be set to the desired level, followed by txen driven high. forward signal transmission is enabled at the resultant gain level.
ADA4320-1 rev. a | page 13 of 16 ramp pin feature output transformer the ramp pin (pin 6) can be optionally used to control the length of the burst on and off transients. by default, leaving the ramp pin unconnected results in a transient that is fully compliant with docsis 3.0. adding capacitance to the ramp pin slows the dissipation even more. matching the 300 differential output impedance to unbalanced 75 requires a 4:1 impedance (2:1 turns) ratio transformer. the transformer should have minimal insertion loss over the 5 mhz to 85 mhz band and have a maximum dc current rating of at least 200 ma. characterization of the ADA4320-1 was performed using a coilcraft pwb-4-bl surface-mount wide-band rf transformer. alternate choices for the output transformer are the toko 458pt-1565 and the tyco electronics (m/a-com) abact0018. gnd gnd vin? vin+ gnd comp vout+ vout? vout+ vout? gnd gnd vcc vcc vcc ramp txen gnd gnd gnd clk daten ADA4320-1 sdata sleep 0.1f 10f lpf qpsk/qam burst modulator dac diplexer to tuner or splitter 0.1f 3-wire (spi-compatible) control power-down control transmit enable/disable control + 5 v 100pf 0.1f 100nh 2:1* upstream downstream f-connector *coilcraft pwb-4-bl alternates: toko 458pt-1565 tyco mabact0018 0 8707-025 1 8 13 20 figure 24. typical application
ADA4320-1 rev. a | page 14 of 16 outline dimensions 122409-b bottom view top view 0.30 0.25 0.20 1.00 0.90 0.80 1 7 8 12 13 19 20 24 5.00 bsc 4.00 bsc pin 1 indicator (chamfer 0.225) 3.75 3.65 3.50 2.75 2.65 2.50 exposed pad seating plane pin 1 indicator 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.50 bsc 0.50 0.40 0.30 forproperconnectionof the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 25. 24-lead lead frame chip scale package [lfcsp_vq] 4 mm 5 mm body, very thin quad (cp-24-5) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ordering quantity ADA4320-1acpz-r7 C40c to +85c 24-lead lead frame chip scale package (lfcsp_vq) cp-24-5 1,500 ADA4320-1acpz-rl C40c to +85c 24-lead lead frame chip scale package (lfcsp_vq) cp-24-5 5,000 ADA4320-1acpz-eval evaluation board 1 z = rohs compliant part.
ADA4320-1 rev. a | page 15 of 16 notes
ADA4320-1 rev. a | page 16 of 16 notes ?2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d08707-0-10/10(a)

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